The present invention relates generally to the field of integrated circuits (ICs) and in particular, to process, voltage, and temperature (PVT) variations in ICs.
PVT variations are one of the critical factors that hamper the performance of the ICs. For example, PVT variations can result in a change in setup and hold times of synchronous circuits. Different components of a synchronous circuit are driven by a common system clock. Therefore, a change in the setup or hold times corresponding to any one component can result in erroneous circuit output. PVT variations can also result in fast switching of signals, which can cause electromagnetic interference (EMI). Further, PVT variations may cause current leakage.
One technique for reducing PVT variations in a circuit is based on sensing variations in the operation of the circuit, and taking appropriate action to reduce these variations. For example, if a variation in the signal delay is identified in the circuit, then the input signal is delayed to compensate for the variation. In other cases, delay variations in the circuit are monitored. Bias voltages of P-metal oxide semiconductor (PMOS) and N-metal oxide semiconductor (NMOS) transistors of the circuit are then changed, depending on the delay variations.
Some of the techniques mentioned above provide the same compensation for PVT variations to both the PMOS and the NMOS transistors. However, PVT variations associated with the PMOS and the NMOS transistors are different. Therefore, the techniques do not compensate for PVT variations sufficiently. Further, a memory is required to compensate for voltage variations. Finally, these techniques involve additional process steps, which are complex in nature.